Conventional switching devices are used in output circuits as shown in FIGS. 5(A), 5(B) and 5(C) for giving control signals to a controlled device included in a programmable controller. In particular, the output circuits shown in FIGS. 5(A), 5(B) and 5(C) employ FETs as output transistors. Referring to FIG. 5(A), an output circuit 101 is of the so-called "source output" type connected to a controlled device 103 having a power supply VD, and an output detector L, i.e., a load, having a first terminal connected to the negative terminal of the power supply VD. The three terminals P, O and M of the output circuit 101 are connected to the positive terminal of the power supply VD, a second terminal of the output detector L, and the negative terminal of the power supply VD, respectively. The output circuit 101 in part comprises a p-channel FET 105 having a source connected through the terminal P to the positive terminal of the power supply VD, and a drain connected through the terminal O to the second terminal of the output detector L. The output circuit 101 further comprises a resistor 107 connected across the source and the gate of the FET 105 to pull up the gate of the FET 105 to the positive terminal of the power supply VD, a photocoupler 109 comprising a phototransistor 109a having a collector connected to the gate of the FET 105 and an emitter connected through the terminal M to the negative terminal of the power supply VD. Additionally, output circuit 101 comprises and an LED 109b that emits light to drive the phototransistor 109a, and an internal circuit 111 comprising a microcomputer or the like to drive the LED 109b of the photocoupler 109 according to a control signal.
In the source output type output circuit 101, a current is supplied from the voltage supply VD through the resistor 107 to the phototransistor 109a of the photocoupler 109. When the internal circuit 111 drives the LED 109b of the photocoupler 109 for light emission a potential difference is induced between the gate and the source of the FET 105 and the FET 105 is turned on. Then, a current is supplied from the power supply VD through the source and the drain of the FET 105 to the output detector L and the controlled device 103 detects the flow of the current through the output detector L to detect the result of control operation of the internal circuit 111.
Referring to FIG. 5(B), an output circuit 121 is of the so-called "sink output" type connected to a controlled device 123 having a power supply VD, and an output detector L having a first terminal connected to the positive terminal of the power supply VD. The three terminals P, O and M of the output circuit 121 are connected to the positive terminal of the power supply VD, a second terminal of the output detector L, and the negative terminal of the power supply VD, respectively. The output circuit 121 in part comprises an n-channel FET 125 having a source connected through the terminal M to the negative terminal of the power supply VD, and a drain connected through the terminal O to the second terminal of the output detector L. The output circuit 121 further comprises a resistor 127 connected across the source and the gate of the FET 125 to pull down the gate of the FET 125 to the positive terminal of the power supply VD, a photocoupler 129 comprising a phototransistor 129a having a collector connected through the terminal P to the positive terminal of the power supply VD and an emitter connected to the gate of the FET 125. Additionally, out put circuit 121 comprises an LED 129b that emits light to drive the phototransistor 129a, and an internal circuit 131 to drive the LED 129b of the photocoupler 129 according to the results of control.
In the sink output type output circuit 121, a current is supplied from the voltage supply VD through the phototransistor 129a of the photocoupler 129 to the resistor 127 when the internal circuit 131 drives the LED 129b of the photocoupler 129 for light emission. Consequently, a potential difference is induced between the gate and the source of the FET 125 and the FET 125 is turned on. Then, a current is supplied from the power supply VD through the drain and the source of the FET 125 to the output detector L and the controlled device 123 detects the flow of the current through the output detector L to detect the result of control operation of the internal circuit 131.
The source output type output circuit 101 switches the current line connecting the power supply VD to the output detector L on the positive side (high side) of the output detector L, the sink output type output circuit 121 switches the current line connecting the power supply VD to the output detector L on the negative side (low side) of the output detector L.
An output circuit 141 shown in FIG. 5(C) is of the so-called "independent output" type capable of being used in either the "source output" type or the "sink output" type. In the configuration shown in FIG. 5(C), the output circuit 141 is in a source output type, in which an output detector L in controlled device 143 is on the negative side of power supply VD. The output circuit 141 is connected through two terminals P and O to the positive terminal of the power supply VD and a second terminal of the output detector L, respectively. The output circuit 141 comprises in part a n-channel FET 145 having a drain connected through the terminal P to the positive terminal of the power supply VD and a source connected through the terminal O to the second terminal of the output detector L. Output circuit 141 further comprises a resistor 147 connected across the gate and the source of the FET 145, a photovoltaic coupler 149 comprising a photodiode array 149a connected in forward connection in the direction from the gate to the source of the FET 145 and in parallel to the resistor 147. Additionally, circuit 141 comprises an LED 149b that emits light to make the photodiode array 149a generate an electromotive force, and an internal circuit 151 that drives the LED 149b of the photovoltaic coupler 149 for light emission according to the result of control.
In this independent type output circuit 141, the photodiode array 149a generates voltage when the internal circuit 151 drives the LED 149b of the photovoltaic coupler 149 for light emission and, consequently, a potential difference is induced between the gate and the source of the FET 145 to turn on the FET 145. Then, a current is supplied from the power supply VD through the drain and the source of the FET 145 to the output detector L, the controlled device 143 detects the flow of a current through the output detector L to detect the result of control operation of the internal circuit 151.
In output circuits 101, 121 and 141, the FETs 105, 125 and 145 are turned on instantaneously and an erroneous output is provided when the controlled devices 103, 123 and 143 are connected with the power supplies VD turned on or when the power sources VD are turned on and the controlled devices 103, 123 and 143 are connected. Consequently, the controlled devices 103, 123 and 143 malfunction. Specifically, trouble occurs because a current If is supplied through the resistors 107, 127 and 147 to the junction capacitances Cgd between the gate and the source of each of the FETs 105, 125 and 145 as shown in FIG. 5. As a result, a potential difference is induced between the gate and the source of each of the FETs 105, 125 and 145, and the so-called flash-on occurs when a voltage that increases sharply is applied across the drain and the source of each of the FETs 105, 125 and 145.
Since the driving ability of the photovoltaic coupler 149 of the independent output type output circuit 141 as shown in FIG. 5(C) is as minute as several tens of microamperes, the resistance of the resistor 147 connected across the gate and the source of the FET 145 must be several hundreds kilo-ohms or above. Therefore, a voltage is generated across the gate and the source of the FET 145 by a slight current and, since the discharge time of the junction capacitance Cgs between the gate and the source is comparatively long, striking flash-on inevitably occurs.
A technique proposed to prevent such flash-on is disclosed in JP-A No. 5-37322 and will be explained in connection with the "sink output" type output circuit shown in FIG. 5(B). For example, in FIG. 6 an output circuit 161 incorporating this prior art technique, is shown. In particular, a capacitor 163 is connected across a terminal P to the positive terminal of a power supply VD and the source of a FET 125. Additionally, a resistor 165 is connected across the junction point between the source of the FET 125 and the capacitor 163, and a terminal M connected to the negative terminal of the power supply VD, and a bypass circuit 167 for bypassing the resistor 165 when the terminal voltage of the capacitor 163 exceeds a predetermined level.
In this output circuit 161, the capacitor 163 is not charged immediately after the connection of a controlled device 123 or the connection of the power supply VD, and hence the potential of the source of the FET 125 is equal to that of the positive terminal of the power supply VD. Then, the capacitor 163 is charged through the resistor 165 with time and the voltage on the side of the source of the FET 125 decreases gradually. Upon the increase of the terminal voltage of the capacitor 163 beyond a predetermined level, the bypass circuit 167 closes to omit the resistor 165 from the line connecting the source of the FET 125 and the negative terminal of the power supply VD. Accordingly, the source-drain voltage of the FET 125 increases gradually when the supply voltage of the power supply VD is applied to the output circuit 161, which prevents the flash-on of the FET 125, i.e., the instantaneous closing of the FET 125.
However, prior art output circuit 161 requires bypass circuit 167 to bypass the resistor 165 inserted in the current line, and generally the bypass circuit 167 is comprised of a relay or a transistor. Alternatively, when the bypass circuit 167 is comprised of a relay, the relay increases the size of the device. When the bypass circuit 167 is comprised of a transistor, the current capacity of the transistor must be equal to or greater than that of the output transistor, i.e., the FET 125, which inevitably increases the size of the device when the resistance of the output detector L, i.e., the load, is small or the supply voltage of the power supply VD is high and a high current flows through the bypass circuit 167.
Those known output circuits 101, 121, 141 and 161 are problematic in that the time necessary to turn off the FETs 105, 125 and 145, i.e., off delay time, is comparatively long. The off delay time is described below with reference to FIG. 7 in connection with the independent output type output circuit shown in FIG. 5(C). In particular, when turning OFF the FET 145 in the ON state, the internal circuit 151 stops the light emitting operation of the LED 149b to stop voltage generation by the photodiode array 149a. Then, as indicated by the two arrows in FIG. 7(A), the gate-source junction capacitance Cgs and the gate-drain junction capacitance Cgd of the FET 145 are discharged through the resistor 147. Subsequently, the gate-source voltage of the FET 145 drops to a predetermined OFF voltage and the drain-source voltage of the FET 145 starts increasing, i.e., the FET 145 starts changing from the ON state to the OFF state. At the same time, a current flows through the resistor 147 to the gate-drain junction capacitance Cgd as indicated by the arrow shown in FIG. 7(B) due to the rise of the drain-source voltage to impede the discharge of the gate-source junction capacitance Cgs. Thus, the OFF delay time is the sum of time T1 in which the junction capacitance Cgs and Cgd of the FET 145 are discharged and the gate-source voltage of the FET 145 drops to the predetermined OFF voltage, and time T2 in which the discharge of the junction capacitance Cgs is impeded by the charging of the gate-source junction capacitance Cgd by the rising drain-source voltage of the FET 145. As a result, this known output circuit cannot reduce the OFF delay time and, consequently, is incapable of rapid switching operation. Furthermore, an output circuit employing a bipolar transistor or an IGBT having both the characteristics of a bipolar transistor and a FET instead of a FET has the same problems.
In view of the foregoing, there is a present need for a switching device of a simple configuration capable of preventing flash-on. Additionally, there is a present need for a switching device capable of reducing the OFF delay time.